Name of participant: Javier Acevedo
Project description:
RISC-ARA: 5G/6G channel estimation hardware acceleration with the RISC-V architecture
Channel estimation for 5G/6G wireless communication systems
The performance of wireless communication systems is highly influenced by the characteristics of the physical channel between transmitters and receivers. In 5G campus networks, where channel conditions vary rapidly for instance, the knowledge about the properties of the channel contributes to reducing fading by adjusting the gain of the power amplifiers at the base stations. In order to identify how a wireless channel affects a modulated signal, a reference signal is sent at the transmitter, and is then correlated with the signal that arrives at the receiver. The process of estimating the characteristics of the channel in terms of amplitude, phase and delay is denoted as Channel Estimation (CE) and employs metrics such as Signal-to-Noise Ratio (SNR), spatial correlation, and doppler shift to derive the Channel State Information (CSI). However, the computation in real-time of the CSI is a complex signal processing operation, which involves multiple matrix multiplication and inversion. In complex systems, composed of massive MIMO antenna pair elements, the number of parameters employed to estimate the CSI increases, making it collectively harder to maintain the accuracy in the calculation of the characteristics of the channel. Hence, hardware-based acceleration rises as a crucial factor to increment throughput and accuracy, while reducing latency.
Hardware acceleration in RISC-V
The computation of the CSI requires the processing of large amounts of data in real-time in order to make the information about the channel valid. In order to adjust the gain of the power amplifiers or to correctly direct the beamforming between the transmitter and the receiver on-the-fly, the processor has to offload those tasks to specialized computing modules, which can fulfill the throughput, reliability and latency requirements. Although general-purpose architectures such as the processors based on the x86 or ARM offer plenty of versatility, they can not properly tackle the computation of intensive algebraic operations due to a fixed Instruction Set Architecture (ISA), high computing frequencies, high data movement overhead and power consumption.
In this context, RISC-V is emerging as a very attractive architecture to develop custom hardware accelerators in different domains. Due to its flexibility, RISC-V allows for customization of the ISA extensions, enabling the development of accelerators tailored to perform channel estimation computations. Furthermore, its modularity leverages the integration of standalone hardware with other modules to extend its functionality in computing physical layer functions. Therefore, in this project, we are designing the ISA extension of a RISC-V processor in order to compute channel estimation kernels, leveraging high throughput and low latency.
The ultimate goal of this research initiative is the development of a fully stack Base Station-on-Chip (BSoC), in which all the physical layer functions can be implemented on a RISC-V-based computing platform.
Software Campus-Partner: TU Dresden & Huawei
Implementation period: 01.03.2023 – 23.08.2025
